The present invention relates to the design of a dual voltage output buffer with compensation circuitry for variations in process and slew rate controlled output switching.
A typical personal computer or work station will have a number of semiconductor chips connected over a common bus. As the need for increased speed continues, the speed of the bus will get faster and faster. Accordingly, when a bus standard is adopted, a number of parameters for connecting to the bus need to be specified. For example, the "slew rate" of switching outputs connected to the bus must be within a specified range. The slew rate is the speed or slope of the signal as it transitions from a low to high or a high to low on the bus. Too fast a transition generates noise on the bus which can affect other devices. In addition, signals on the bus are often specified to have a required current drive capability. An example of such a bus is the 3.3 volt 66 MHZ PCI bus. The PCI standard specifies a slew rate range which must be met. To meet this, transistors must be sized to be fast enough, yet not be too fast and cause noise.
As integrated circuit chips become more and more dense, with transistor dimensions becoming smaller and smaller, it becomes increasingly difficult to control the characteristics of the devices. The amount of current produced by a transistor, which will affect the rate at which it will transition, and thus its slew rate, is affected by a number of factors. This current is given by the equation I=K(W/L)(Vgs-Vt).sup.2, where I=current, K=a constant dependent upon the process, W=the width of the transistor, L=the length of the transistor, Vgs=the gate-source voltage of the transistor, and Vt=the threshold voltage of the transistor. Although the width and length of the transistor can be specified for desired current drive capability, and the voltage across it can be designed to provide the desired gate-source voltage, the process dependent factor K can vary widely. This is due to the doping to create the P and N regions in the transistors being a chemical process done over a period of time, and from wafer to wafer the actual characteristics can vary based on slight variations in concentration and process time, which have a magnifying effect for a very small device size. Variations of up to 70% are typical.
One prior method for controlling the slew rate in drives uses staggered transistors, with each switched on a delayed amount of time later than the previous ones to limit the ramping. Another method involves using a bandgap reference circuit, counters, and an external resistance to determine if the process is a fast or slow process, and provide appropriate compensation using digital control. In one example, extra transistors in parallel can be provided, and can be switch connected or not depending on process variations. Clearly, such a method involves a significant amount of circuitry.
Additional design complications arise as designers attempt to make integrated circuits which operate with lower and lower voltage supplies to reduce power consumption and increase internal clock speed by having the transition shortened by shortening the levels to which the voltage must transition to. For example, circuits which operate on a 2.5 volt internal design are being designed. However, a difficulty is encountered when these circuits must interface with a bus which is standardized at a higher voltage, such as 3.3 volts.